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this is a summary document. the complete document is available under nda. for more information, please contact your local atmel sales office. 9208fs-rke-06/13 features supported frequency ranges low-band 310mhz to 318mhz, 418mhz to 477mhz high-band 836mhz to 928mhz 315.00mhz/433.92mhz/868.30mhz and 91 5.00mhz with one 24.305mhz crystal low current consumption 9.3ma for rxmode (low-band) 480 a for 50ms cycle 3 channel polling 9.1ma/13.8ma for txmode (low-band, pout = 6dbm/10dbm) typical offmode current of 5na (max. 600na at vs = 3.6v and t = 85c) programmable output power ?12dbm to +14.5dbm (0.4db step) input 1db compression point ?35dbm (full sensitivity level) ?20dbm (15db reduced sensitivity) programmable channel frequency with fractional-n pll 93hz resolution for low-band 185hz resolution for high-band fsk deviation 0.375khz to 93khz fsk sensitivity (manchester coded) at 433.92mhz ?106dbm at 20kbit/s, f=20khz, bw if = 165khz ?109dbm at 10kbit/s, f=10khz, bw if = 165khz ?112dbm at 5kbit/s, f = 5khz, bw if = 165khz ?121dbm at 0.75kbit/s, f = 0.75khz, bw if =25khz ask sensitivity (manchester coded) at 433.92mhz ?107dbm at 20kbit/s, bw if = 366khz ?117dbm at 1kbit/s, bw if = 366khz programmable rx-if bandwidth 25khz to 366khz (approx. 10% steps) blocking (bw if = 165khz): 64dbc at freq. offset = 1mhz and 48dbc at 225khz high image rejection 55db (315mhz/433.92mhz) 47db (868.3mhz/915mhz) without calibration supported buffered data rate 0.5kbit/s to 20kbit/s (higher data rates up to 80kbit/s manchester coded and 160kbit/s nrz with transparent data in/output) supports pattern based wake-up and start of frame identification digital rssi with very high relative accuracy of 1db due to digitized if processing ata5830/ata5830n uhf ask/fsk transceiver summary datasheet
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 2 programmable clock output derived from crystal frequency 24kb rom with atmel firmware and integrated avr ? microcontroller for control 6kb in system self programmable flash for an additional customer application software 512 byte eeprom data memory for transceiver configuration and 768 byte sram spi interface for rx/tx data access and transceiver configuration configurable event signal indicates the status of the ic automatic antenna tuning at tx center frequency for loop antenna automatic low power channel polling (3 rke channels, tpms, rs) id scanning up to 18 different ids with 1..4 byte supply voltage ranges 1.9v to 3.6v and 4.5v to 5.5v temperature range ?40c to +105c esd protection at all pins (4kv hbm, 200v mm, 750v fcdm) small 5mm 5mm qfn32 package/pitch 0.5mm suitable for applications governed by en 300 220 and fcc part 15, title 47
3 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 1. general product description 1.1 overview the atmel ? ata5830 is a highly integrated, low power uhf ask/fsk rf-transceiver. the atmel ata5830 is partitioned into several sections; an rf frontend, a digi tal baseband, and a low power 8 bit avr microcontroller. the product is designed for the ism frequency bands in the ranges of 310 to 318mhz, 418 to 477mhz and 836 to 928mhz. external part count is kept to a minimum due to the very high level of integration in this device. by combining outstanding rf performance with highly sophisticated baseband signal processing, robust wireless comm unication can be easily achiev ed. the receive path uses a low-if architecture with an integrated double quadrature receiv er and digitized if processing. this results in high image rejection and excellent blocking performance. the transmit path uses a closed loop fractional-n modulator with gaussian shaping and pre-emphasis functionality for high data rates. in ad dition, the highly flexible and configurable baseband signal processing allows the transceiver to operate in several scanning, wake-up and automatic self polling scenarios. for example, during polling the ic can seek ce rtain message content (ids) and save valid telegram data in the fifo buffer for later retrieval. the device possess two receive paths that enable parallel search for two telegrams with different modulations, data rates, wake-up conditions , etc. the highly configurable and autonomous scanning capability enables polling of up to five application channels such as 3-channel rke, tpms, peg. th e configuration of the transceiv er is stored in a 512 byte eeprom. the spi allows for external control and reconfiguratio n of the device. the internal microcontroller and 6 kb flash can be used to add customer extensions to the atmel fi rmware. the debug wire and isp interface are available for programming purposes. 1.2 target applications the transceiver is designed to be used in the following application areas: remote keyless entry system (rke) passive entry go system (peg) tire pressure monitori ng system (tpm,tpms) remote start system (rs) remote control system, e.g. garage door open smart rf applications telemetering systems three applications with a total of 5 channels are support ed by the atmel firmware for autonomous self polling. 1.3 main extended features of the atmel ata5830 1.3.1 rf performance the atmel ata5830 provides high sensit ivity and programmable transmit power up to 14dbm. the high image rejection and outstanding blocking performance enable a robust application agai nst interferer with a low cost design. in addition, the programmable channel filter bandwidth provides fl exibility to adapt to vari ous system requirements. 1.3.2 automatic self polling and multi channel capability the autonomous self polling supports the automatic scanning for th ree different applications such as remote keyless entry (rke), tire pressure monitoring system (tpms) and remote start (rs) using one ic. additionally multi channel systems with up to three frequencies can be scanned. this means fi ve frequencies can be scanned in the autonomous polling scheme; three for rke, one for tpms and one for rs. the conf iguration of each application is independent of the others. this is possible because of the flexibility in the digital baseband and two different baseband receiving paths. the ic can immediately scan all applications upon power-up without the need for any initial configuration by an external microcontroller. 1.3.3 wake-up scenario and id scanning the powerful bas eband signal processing is designed to offload these time co nsuming tasks from the host controller. this allows the transceiver to discard unwanted telegrams and limit external microcontroller wake up to valid telegrams only. up to 7 criteria can be used to determine the te legram validity from carrier check on the lowest level to start of frame id patter n match at the highest level.
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 4 1.3.4 two parallel receiving paths the transceiver?s baseband contains two data paths. the para meters of both paths can be set differently, e.g. the modulation type or data rate. generally bot h paths are working simultaneously but only the first path detecting a valid telegram will be used for further data reception and filling of the 32 byte buffer. the 32 byte receive data buffer can be accessed using spi commands from the external host microcontroller. 1.3.5 channel statistic in order to accelerate the communication in multi channel applications the atmel ata583 0 offers a feature defined as channel statistic. if this feature is selected, the ic will find the best channel within the three rke channels (with regard to interference) and automatical ly select the best channel for the first transmission. 1.3.6 antenna tuning and spdt for applications using a loop antenna, the atmel ata5830 offe rs an automatic antenna tuning feature which improves the antenna performance by compensating for ?hand effects? or matching component value variations. the integrated spdt acts as rx/tx switch which eliminates the cost of an external rx/tx switch. 1.3.7 customer application software all the functionality is implemented in 24kb of rom firmware and controlled by spi commands. in addition, 6kb of flash is available to enable customer specific software functionality. examples for flash customizat ion are a) extension of spi commands, b) usage of a single wire interface instead of spi, c) polling adaptations, d) protocol handling, etc. to achieve customer specific functionality, parts of the rom code can be replaced with flash code. 1.3.8 eeprom configuration the configuration of the device e.g. rf-frequency, modulation ty pe, data rate, etc. is stored in 512byte of eeprom that is integrated within the atmel ? ata5830. this improves the efficiency of the spi control since most of the configuration comes from the eeprom. in most applications, only the received or transmitted data and short spi command s are required. the device is delivered with a standard configurat ion; only deviations from that need to be configured. device configuration uses only a part of the 512byte of eeprom leaving free space availa ble for additional cust omer data storage. a modification of the eeprom content is only allowed during idlemode.
5 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 1.4 pin diagram and configuration of atmel ata5830 figure 1-1. pin diagram note: the exposed die pad is connected to the internal die. table 1-1. pin configuration pin no. pin name type description 1 rfin_lb analog rxmode, lna input for low-band frequency range (< 500mhz) 2 rfin_hb analog rxmode, lna input for high-band frequency range (> 500mhz) 3 spdt_rx analog rxmode output of the spdt s witch (damped signal output) 4 spdt_ant analog antenna input (rxmode) and output (txmode) of the spdt switch 5 ant_tune analog antenna tuning input 6 spdt_tx analog txmode input of the spdt switch 7 rfout analog power amplifier output 8 vs_pa analog power amplifier supply - 3v application supply voltage input - 5v application internal voltage regulator output 9 test_en - test enable, connected to gnd in application 10 xtal1 analog crystal oscillator pin1 (input) 11 xtal2 analog crystal oscillator pin2 (output) 12 avcc analog rf frontend supply regulator output 13 vs analog main supply voltage input 14 pc0 digital main: avr port c0 alternate: pcint8 /nreset/debug wire 15 pc1 digital main: avr port c1 alternate: npwron1/pcint9 16 pc2 digital main: avr port c2 alternate: npwron2/pcint10/trpa rfin_lb rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 test_en spdt_rx spdt_ant ant_tune spdt_tx rf_out vs_pa pb2 32 1 2 exposed die pad 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 9 10111213141516 pb1 pb0 dgnd dvcc pc5 pc4 pc3 atmel ata5830 atest_io2 atest_io1
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 6 17 pc3 digital main: avr port c3 alternate: npwron3/pcint11/tmdo/txd 18 pc4 digital main: avr port c4 alternate: npwron4/pcint12/int0/ tmdi/rxd 19 pc5 digital main: avr port c5 alternate: npwron5/pcint13/trpb/ tmdo_clk 20 dvcc - digital supply voltage regulator output 21 dgnd - digital ground 22 pb0 digital main: avr port b0 alternate: pcint0/clk_out 23 pb1 digital main: avr port b1 alternate: pcint1 / sck 24 pb2 digital main: avr port b2 alternate: pcint2/mosi (master out slave in) 25 pb3 digital main: avr port b3 alternate: pcint3/miso (master in slave out) 26 pb4 digital main: avr port b4 alternate: pwron/pcint4/led1 (strong high side driver) 27 pb5 digital main: avr port b5 alternate: pcint5/nss 28 pb6 digital main: avr port b6 alternate: pcint6 /event (firmware c ontrolled external microcontroller event flag) 29 pb7 digital main: avr port b7 alternate: npwron6/pcint7/ rx_active (strong high side driver)/ led0 (strong low side driver) 30 agnd - analog ground 31 atest_io2 - rf frontend test input/ output 2, connected to gnd in application 32 atest_io1 - rf frontend test input/ output 1, connected to gnd in application gnd - ground/backplane on exposed die pad table 1-1. pin configuration (continued) pin no. pin name type description
7 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 1.5 typical application circuits figure 1-2. typical 3v application with external microcontroller figure 1-2 shows a key fob application circuit with an external hos t microcontroller for 315mhz or 433.92mhz running from a 3v lithium cell. the atmel ? ata5830 stays in offmode until nss(pb5) and npwron1(pc1) are used to wake it. in offmode the atmel ata5830 draws typically le ss than 5na (600na maxi mum at 3.6v/85c). in offmode all atmel ata5830 avr ? ports pb0..pb7 and pc0..pc5 are switched to input. pc0..pc5 and pb7 have internal pull-up resistors ensuring that the voltage at these ports is vs. pb0..pb6 are tris tate inputs and require additional consideration. pb1,pb2 and pb5 have defined voltages sinc e they are connected to the output of the external microcontroller. pb4 is connected to ground to avoid unwant ed power ups. pb0, pb3 and pb6 do not require external circuitry since the internal circuit avoids transverse currents in the offmode. the external microcontroller has to tolerate th e floating inputs. otherwise additional pull down resistors are required on these floating lines. typically, the key fob buttons are connected to the external microcontroller and the atmel ata5830 wake-up is done by pulling nss (pin 27) and npwron1 (pin 15) to ground. if there are not enough ports for button inputs on the microcontroller, it is possible to connect up to four additional buttons to th e ports pc2..pc5. in this case, the occurrence of a port event (button pressed) will generate an interrupt (pin 28). the port event that triggered the interrupt is available in the event register. in this type of application a pcb trace loop antenna is typi cally used. an internal antenna tuning procedure tunes the resonant frequency of this loop antenna to the tx frequency. this is accomplished with an integrated variable capacitor on the ant_tune pin. rf_out and rf_in are optimally matche d to the spdt_tx and spdt_rx pins of the integrated rx/tx switch. the spdt_ant pin has an impedance of 50 for both the rx and tx functions. the dc output voltage of the power amplifier is required at the spdt_tx pin for proper opera tion. also, the rfin pin needs a dc path to ground, which is easily achieved with the matching shunt inductor. th e impedance of the loop antenna is transformed to 50 with three capacitors, two of them external and one built into the atmel ata5830 on the ant_tune pin. an external crystal, together with the fractional-n pll within the atmel ata5830 is used to fix the rx and tx frequency. accurate load capacitors for this crystal are integrated, to reduce system part count and cost. only four supply blocking capacitors are needed to decouple the different supply vo ltages avcc, dvcc, vs and vs_pa of the atmel ata5830. the exposed die pad is the rf and analog ground of the atmel ata583 0. it is directly connected to agnd via a fused lead. for applications operating in the 868.3mhz or 915mhz frequency bands , a high band rf input is supplied, rfin_hb, and must be used instead of rfin_lb. rfin_lb irq nss miso mosi sck vdd clk_in atest _io1 atest _io2 test _en rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 spdt_rx spdt_ant ant_tune spdt_tx rf_out vs_pa pb2 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 910111213 1415 16 pb1 pb0 dgnd dvcc pc5 pc4 pc3 vs = 3v microcontroller atmel ata5830
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 8 the atmel ata5830 is controlled using specific spi comm ands via the spi interface and an internal eeprom for application specific configuration. figure 1-3. typical 3v stand alone application figure 1-3 shows a standalone key fob application circuit for 315m hz or 433.92mhz running from a 3v lithium cell. the atmel ? ata5830 stays in offmode until one of the npwron po rts pc1..pc5 are pulled to ground level and therefore waking up the circuit. the npwron ports pc1..pc5 have internal 50k pull-up resistors and can be left open if not used. application software within the 6kb flas h is used to control the atmel ata5830 t ogether with firmware in the 24kb rom. the rf and decoupling circuitry is similar to figure 1-2 on page 7 . in this application, an led is connected to pb7 (alternatively, an additional wake -up button can be used on pb7 instead of an led). an led can also be connected to pb4. however, note the additional pull-down resistor connected in parallel that is needed to prevent transverse currents in offmode. this s pecial case applies to pb4 because of its active input characteristics (pwron). rfin_lb atest _io1 test _io2 test _en rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 spdt_rx spdt_ant ant_tune spdt_tx rf_out vs_pa pb2 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 910111213 141516 pb1 pb0 dgnd dvcc pc5 pc4 pc3 vs = 3v vs atmel ata5830 vs vs
9 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 figure 1-4. typical 5v application circuit with external microcontroller figure 1-4 shows a typical vehicle side application circuit with an external host microcontroller running from a 5v voltage regulator. in contrast to the 3v application with external microcontroller, the pin pb4 (pwron) is directly connected to vs and the atmel ? ata5830 enters the idlemode after power on. in this configuration the atmel ata5830 can work autonomously while the microcontroller stays powered down to ac hieve low current consumption while being sensitive to rf telegrams. to achieve low current in idlemode the atmel ata5830 can be configured in the eeprom to work with the 125khz rc oscillator (this mode is named idlemo de(rc)). the atmel ata5830 can also be configured for autonomous multi channel and multi application pollingmode(rc). the external microcontrolle r is notified with irq if an appropriate rf message is received. until that takes place, the atmel ata5830 periodic ally switches to rxmode, checks the different channels and applications configured in the eeprom and returns to the idlem ode(rc) all the while with the external host avr ? microcontroller in a deep sleep mode to achieve a low avera ge current while being polling for valid rf messages. once a valid rf message is detected, it can be buffered within the atmel ata5830 to allow the microcontroller time to wake-up and retrieve the buffered data. in applications that use the 4.5 to 5. 5v supply (vs), it is important to not e that only atmel ata5830 ports pb0..pb7, pc0..pc5 and the external host microcontroller use this supply. the power amplifier of the atme l ata5830 is limited to 3.6v therefore an internal ldo delivers 2.7v to 3.3v supply volt age in txmode on pin vs_pa. the capacitor on pin vs_pa is needed to stabilize this regulator and decouple the power amp lifier supply voltage. the ports pc0..pc5 have internal 50k pull-up resistors and can be left open. the ant_tune pin must be left open. as in the 3v applications, rf_out and rf_in are matched to spdt_tx and spdt_rx by absorbing the parasitics of the spdt switch into the matching netw ork, hence the spdt_ant is a 50 rx and tx port. the impedance of the saw filter is transformed with lc matching circuits to the spdt_ant port and also to the antenna. care has to be taken to insure the transmit power going through the saw does not exceed it s power handling capability. the series capacitor on pin spdt_ant is needed because the dc voltage on this pin is se t to vs_pa/2 voltage in txmode and saw filters normally should not be subjected to a dc voltage. alternatively, the saw can also be inserted between spdt_rx and rf_in. in this case, special care for spurious and harmonics of the tx signal is required. rfin_lb irq nss miso mosi sck vdd clk_in atest _io1 atest _io2 test _en rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 spdt_rx spdt_ant ant_tune spdt_tx rf_out vs_pa pb2 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 910111213 1415 16 pb1 pb0 dgnd dvcc pc5 pc4 pc3 vs = 5v vs saw microcontroller atmel ata5830
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 10 figure 1-5. typical 5v application circuit with one wire control figure 1-5 shows a typical vehicle side application circuit runni ng from a 5v voltage regulat or delivered from the lin transceiver ata6625 device. the applicati on can be directly connected to vehicle's wiring harness. in this case, the pin pb4 (pwron) is directly connected to vs and the atmel ? ata5830 enters the idlemode upon power up of the ata6625 and stays there after the software in the flash asserts the en pin on ata6625 to high. the system can be completely switched on or off with a command over the one wire bus. this applicati on is used when the external host microcontroller must be separated over a distance from the atme l ata5830 such as systems having remote antennas integrated into window glass. in these situations, the atmel ata5830 can work autonomously and communicate to external host microcontroller on a 1 wire bus. the application software within the 6kb flash, together wi th 24kb rom firmware, is used for the control of the atmel ata5830 and atmel ata6625. a simplified lin compliant physical layer can be used for one wire communication. the atmel ata5830 does not natively support one wire commands. howe ver, through the use of applic ation flash software one wire communication can be achieved. please refer to the note in the previous example ( figure 1-4 on page 9 ) regarding the use of a 4. 5 to 5.5v supply and its distribution within the atmel ata5830. ports pc0..pc2 have internal 50k pull-up resistors and can be left open. but, ports pb1, pb2 and pb5 must be connected to ground. the ant_tune pin has to be left open. notes about rf decoupling and supply circuitry are the same as application shown in figure 1-4 on page 9 . rfin_lb rxd txd nres vcc lin gnd en vs atmel ata6625 lin atest _io1 atest _io2 test _en rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 spdt_rx spdt_ant ant_tune spdt_tx rf_out vs_pa pb2 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 910111213 141516 pb1 pb0 dgnd dvcc pc5 pc4 pc3 vs = 5v 12v battery vs saw atmel ata5830 vs +
11 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 1.6 system overview figure 1-6. circuit overview figure 1-6 shows an overview of the main functional blocks of the atmel ata5830. the cont rol of the atmel ata5830 is performed through the spi pins sck, mos i, miso and nss found on port b. the co nfiguration of the atmel ata5830 is stored in the eeprom and a large part of the functionality is defined with the firmware located in the rom and processed using the avr ? . e.g. a spi command like ?start rxmode? uses the information loca ted in the eeprom configures all hardware registers of the differ ent blocks according to this in formation, starts then the rxmode and directs the received data to the rx buffer located in the sram. an event on port pb6 is signaled to the external microcontroller when the expected number of bytes are received. part of the eeprom content is copied to the sram during star t-up of the atmel ata5830 for fa ster access. care should be taken to limit eeprom r/w cycles so that the device's maximum rating is not exc eeded. alternat ively, the user should consider modifying the parameters in the sram. it is important to not e that pwron and npwron pins are active in offmode. this means that even if the atmel ? ata5830 is in offmode and the dvcc voltage is switched off, power management circuitry within the atmel ata5830 will bias these pins with vs. avr ports can be used as button inputs, external lna supply voltage (rx_active), led driver, event pins, switching control for additional spdt switches, general purpose digital input s, wake up inputs etc. some functionality of these ports is already implemented in th e firmware and can be activated with eeprom configuration. other func tionality is possible only through custom software residing in the 6kb flash program memory. 1.7 compatibility to the atmel uhf receiver ata5780 the transceiver atmel ata5830 is pin compatible to the rece iver ata5780. the receiver has the identical rx performance of the transceiver rx path. the difference exists in the digital block only. while ex tremely flexible, the receiver operates as a statemachine and its functionality is limit ed to user selectable eeprom configuratio n options. as a result, the receiver is fully compatible with the transceiver but without the flexibility of 6kb flash program space for custom applications. rx dsp rf frontend tx dsp rfin rfout data bus src, frc oscillators port b (8) xto xtal pb (0 to 7) (spi) pc (0 to 5) vs avcc dvcc port c (6) avr perepherals avr cpu supply reset sram rom flash eeprom
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 12 2. system operation modes the scope of this section is to give an overview of the atmel ? ata5830 supported operation modes, shown in figure 2-1 . figure 2-1. operation modes overview after connecting the supply voltage to the vs pin, the atmel at a5830 always starts in offmode. all internal circuits are disconnected from the power supply. th erefore no spi communication is supporte d. the atmel ata5830 can be woken up by activating the pwron pin or one of the npwronx pins . this triggers the power-on sequence. after firmware initialization the atmel ata5830 reaches the idlemode. the idlemode is the basic system mode supporting spi communi cation and transitions to all other operation modes. there are two options of the idlemode to be configured in the eeprom settings: idlemode(rc) with low power consumption using the fast rc (frc) oscillator for processing idlemode(xto) with active crystal oscillator for hi gh accuracy clock output or timing measurements the transmit mode (txmode) allows for data transmission on o ne of the preconfigured channels for e.g. rke, tpm, rs. it is usually enabled by spi command, or directly afte r power-on, when selected in the eeprom setting. the receive mode (rxmode) provides data reception on one of the preconfigured channels. the precondition for data reception is a valid preamble. the receiver is continuously searching for a valid telegram and receives the data if all preconfigured checks are successfully passed. the rxmode is us ually enabled by spi command, or directly after power-on, when selected in the eeprom setting. in pollingmode the receiver is activated fo r a short period of time to check for a valid telegram on the selected channels. the receiver will be deactivated if no valid telegram is found a nd a sleep period with very low power consumption elapses. this process is repeated periodically according to the eeprom conf iguration. up to 5 channels and a wide range of sleep times are supported by the atmel firmw are. this mode is activated via an spi command, or directly after power-on, when selected in the eeprom setting. the tune and check mode (tcmode) offers a calibration and se lf-checking functionality for the vco and frc oscillators as well as for the ante nna tuning and polling cycle accuracy. th is mode is activated via an spi command. when selected in the eeprom settings the tcmode is used during system initialization after pow er-on. furthermore, the tcmode can be activated periodically during pollingmode. pollingmode txmode init done power-on wdr idlemode rxmode system initialization offmode tcmode extr
13 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 table 2-1 shows the relations between the operation modes and it s corresponding power supplies, clock sources and sleep mode settings. table 2-1. operation modes versus supplies and oscillators operation mode avr sleep mode dvcc avcc vs_pa xto src frc offmode - off off off off off off idlemode(rc) active mode power-down (1) on off off off off off off on on on off idlemode(xto) active mode power-down (1) on on off off on on on on off off txmode active mode on on (2) on on off rxmode active mode on off on on off pollingmode(rc) - active period - sleep period active mode power-down (1) on off off off on off on on on off pollingmode(xto) - active period - sleep period active mode power-down (1) on on off off on on on on off off notes: 1. during idlemode(rc) and idlemode(xto) the avr mi crocontroller will enter a sleep mode to reduce the current consumption. the sleep mode of the micr ocontroller section can be defined in the eeprom. to achieve the optimum curr ent consumption the power-down mode is recommended. 2. only activated at 5v applications. th is is selectable in the eeprom setting.
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 14 3. hardware description 3.1 overview figure 3-1. system block diagram figure 3-1 shows the system block diagram of atmel ? ata5830. in rxmode the crystal oscillator (xto) together with the fractional-n pll generates the local oscillator (lo) signal.the rf signal coming either from the lowband input (rfin_lb) or high band input (rfin_hb) is amplified by the low noise amplifier (lna) and downconverted by the mixer to the intermediate freque ncy (if) using the lo signal. afterwards the if signal is sampled using a high resolution analog to digital converter (adc). within the rx digital signal processing (rxdsp) the received signal from the adc is filtered by a digital channel filter and demodulated. two data receive paths are included into the rxdsp after the digital channel filter . the receive path can also be configured to provide the digital output of an interna l temperature sensor (temp( )). in txmode the fractional-n pll generates the tx frequency. the power amplifier generates a programmable rf output power of ?10dbm to 14dbm on rfout. the fsk modulation is performed by changing the frequency setting of the fractional-n pll dynamically with the tx digital signal pr ocessing (txdsp). digital pre-emphasis and digital gauss filtering can be activated in the txdsp for higher data rates or low occupied bandwidth. the ask modulation is performed by switching the power amplifier on and off. with the single pole double throw (spdt) switch the rf si gnal from the antenna is switched to rfin in rxmode and from rfout to the antenna in txmode. an adjustable capacitor and an rf leveldetector on ant_tune is used to tune the center frequency of loop antennas to reduce tolerances and capacitive proximity effects. lna, mixer power amplifier rx dsp adc rf frontend rfin_lb rfin_hb rfout vs_pa spdt_rx spdt_ant spdt_tx ant_tune tx dsp te m p ( ? ) xto xtal1 xtal2 pb (0 to 7) data bus pc (0 to 5) irq crc avcc dvcc vs rom avr cpu flash eeprom sram watchdog timer src, frc oscillators clock man. debug wire nvm controller port b (8) spi port c (6) ssi modulator rf frontend control 16 bit timers 2x 8 bit timers 3x fractional n-pll power management spdt damping antenna tuning
15 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 the system is controlled by an avr ? cpu with 24kb rom, 6kb flash, 512byte eeprom, 768 byte sram and other peripherals supporting the transceiver handling. two ports pb[0..7] and pc[0..5] are available for external digital connections, e.g. the spi interface is connected to port b. the atmel ? ata5830 is controlled by eeprom configuration and spi commands. the functional behavior is mainly determined by the firmware in the rom. it can be configured to a high degree by modifying the eeprom settings. the firmware running on the avr gives a ccess to the hardware functionality of the atmel ata5830. extensions to this firmware can be added in the 6 kb of flash memory. the rxdsp and txdsp registers are directly accessible from the avr since these dsp?s are directly connected to the avr data bus. the rf frontend registers are programmed with an on chip serial interface(ssi) accessing t he rf frontend control. the power management contains low-dropout (ldo) regulators an d reset circuits for the supply voltages vs, avcc, dvcc and vs_pa of the atmel ata5830. in offmode all the supply voltages avcc, dvcc and vs_pa (vs_pa only for 4.5v to 5.5v operation) are switched off to achieve a very low curr ent consumption. the atmel ata5830 can be powered up by activating the pwron pin or one of the npwron1..6 pins since they are still active in offmode. the rf frontend circuits and the xto are connected to av cc, the avcc domain can be switched on and off independently from dvcc. atmel ata5830 provides two idle modes. in idlemode(rc) only the dvcc voltage regulator, the frc and src oscillators are active and the avr uses a power down mode to achieve a low current consumption. the same power down mode can be used during the inactive phases of the pollingmode. in idlemode(xto) the avcc voltage domain as well as the xto are activated additionally. an integrated watchdog timer is available to restart the atmel ata5830. 3.2 receive path 3.2.1 overview the receive path consists of a low noise amplifier (lna), mi xer, analog-to-digital converter (adc) and a rx digital signal processor (dsp) as shown figure 3-1 on page 14 . the fractional-n phase locked loop (pll) and the quartz oscillator (xto) described above delivers the local oscillator frequency f lo in rxmode. the receive path is controlled with the rf frontend registers. two separate lna inputs, one for low-band and one for high-ba nd, are provided to obtain optimum performance matching for each frequency range and to allow multi band applications. a radio frequency (rf) level detector at the lna output and a switchable damping included into single-pol e double-trough (spdt) switch is used in the presence of large blockers to achieve better system blocking performance. the mixer converts the received rf signal to a low inte rmediate frequency (if) of about 250khz. a double quadrature architecture is used for the mixer to achieve high image rejection. additionally, the 3 rd order suppression of local oscillator (lo) harmonic receiving will make receivi ng without a frontend saw filter, for example in a car keyfob application, less critical. the adc converts the if signal into the digital domain. due to the high effective resolution (14bit) of the used adc the channel filter and rssi can be realized in the digital signa l domain and no analog gain control (agc) which can lead to critical timing issues or analog filtering is required in front of the adc. this leads to a receiver frontend with good blockin g performance up to the 1db compression point of the lna a nd mixer, and a steep digital channel filters can be used. the rx dsp performs channel filtering and converts the digital output signals of t he adc to the baseband for demodulation. due to the digital realization of these functions the rx dsp can be adapted to the needs of many different applications since channel bandwidth, data rate, modulation type, wake-up criteria, signal checks, clock recovery and many other properties are configurable. see rx dsp description in section 3.2.2 ?rx digital signal processing (rx dsp)? on page 16 . a received signal strength indicator (rssi) value is built within the rx dsp completely in the digital signal domain allowing for a high relative rssi accuracy and a good absolute accuracy, which is only deteriorated by the gain errors of lna, mixer and adc. two independent receive paths a and b are integrated in the rx dsp after the channel filter see section 3.2.2 ?rx digital signal processing (rx dsp)? on page 16 and allow the use of different data rate , modulation type and protocol without the need to power up the receive path more than once to decide which signal should be received. this allows a much lower polling current in several applications.
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 16 the integration of remote keyless entry (rke), passive entry and go (peg) and tire pressure moni toring systems (tpm) into one module is simplified since completely different protocols can be supported and a low polling current is achieved. it is even possible using different receive rf bands for different applications by using the two lna inputs. for example a tpm receiver can be realized at 433.92mhz while a peg system uses the 868mhz ism band with multi channel bidirectional communication. 3.2.2 rx digital signal processing (rx dsp) the rx dsp block performs the digital signal processing, decoding and checking of the rx samples from the adc. it delivers the raw data at the trpa/b pins, the decoded data at the tmdo output and the buffe red data bytes (rx byte a/b) from the rx buffer. it also provides auxiliary information about the si gnal like the received signal strength indication (rssi) and the frequency offset of the received signal ve rsus the selected center frequency (rxfoa/b). figure 3-2. rx dsp overview the channel filter determines the receiver bandwidth. its output is used for both receiving paths a and b. therefore it has to be configured to be suitable for both. the receiving paths a and b are identica l and consist of an ask/fsk demodulator with attached signal checks, a frame synchronize r supporting pattern based search for the telegram start and a 1 byte hardware buffer for received data. the receiver architecture with parallel receiving paths a and b allows for a simultaneous search for two different transmitters. the simultaneous search is supported only w hen the flexible telegram support is enabled (see eeprom description). e.g. path a can be configured for an ask telegram with high data rate and path b can be configured for an fsk telegram with low data rate. during pollingmode both settings are appl ied and the check occurs simultaneously. this results in a shorter active time during polling. tmdo_a tmdo_clk_a tmdo_b rxfob trpb rxfoa trpa rssi tmdo_clk_b rx byte a rx byte b demod & check a demod & check b rx buffer a rx buffer a frame sync a frame sync b = = channel filter adc data
17 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 3.3 transmit path 3.3.1 overview the atmel ? ata5830 integrates a transmitter that is ca pable of sending data with various options: frequency bands 310mhz ? 318mhz, 41 8mhz ? 477mhz, 836mhz ? 928mhz data rates up to 80kbit/s manchester or 160ksym/s nrz in transparent mode ask or fsk modulation transparent or buffered mode gauss-shaping digital filter this section describes the hardware blocks that are integrated to perform the tran smit functionality. figure 3-3 shows a block diagram of the transmit data path. figure 3-3. transmit data path the transmission data source can be selected from a register bit, a transparent input pin 18 (tmdi) and an internal 32 byte buffer. if ask/ook modulation is selected t he data stream is used to directly switch on and off the power ampl ifier. the transmitted carrier frequency is set by the frequency synthesizer pll. if fsk modulation is selected the data stream is used to switch between two frequencies that are generated by the frequency synthesizer pll. the power amp lifier is constantly on. to reduce the occupied bandwidth a digital gauss filtering can be enabled. for data rates above 20khz manchester or 40kh z nrz-coding a digital pre-emphasis filter has to be enabled to compensate for the pll loop filter. tdfcr gacdivh gacdivl gauss filtering power amp pll on/off tdcr.gaen ffreq2 h/l/m fsk 1 1 ask 0 00 01 10 11 0 tdcr.txms tdcr.txmod timer modulator ffreq1 h/l/m tdcr.sfm mout4tx so4tx pin 18/ tmdi tdcr.peen tx dsp analog frontend modulation source selection tdcr.sfm tdcr.sdpu tdcr.sden pre- emphasis filtering 1 0 1 0
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 18 3.4 avr controller 3.4.1 cpu core figure 3-4. cpu core overview rx dsp rf frontend rfin_lb rfin_hb rfout vs_pa spdt_rx spdt_ant spdt_tx a nt_tune tx dsp xto xtal1 xtal2 pb(0 to 7) data bus pc(0 to 5) irq crc avcc dvcc vs rom avr cpu flash eeprom sram watchdog timer src, frc oscillators clock man. debug wire nvm controller port b(8) spi port c(6) ssi modulator 16 bit timers 2x 8 bit timers 3x power management
19 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 3.4.1.1 architectural overview this section discusses the avr ? core architecture in general. the main function of the cpu core is to ensure correct program execution. therefore it must be able to access me mories, perform calculations, control peripherals, and handle interrupts. figure 3-5. archit ectural overview in order to maximize performance and parallelism, the avr uses a harvard arch itecture ? with separate memories and buses for program and data. instructions in the program memo ry are executed with a single level pipelining. while one instruction is being executed, the next in struction is pre-fetched from the program memory. this co ncept enables instructions to be executed in every clock cycle. the program me mory is in- system repr ogrammable flash memory. the fast-access register file contains 32 x 8-bit general pu rpose working registers with a si ngle clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu o peration, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect a ddress register pointers for data space addressing ? enabling efficient address calculations. on e of these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16 -bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operat ions between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional ju mp and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit wo rd format. every program memory address contains a 16- or 32-bit instruction. program memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write pr otection. the spm (store progr am memory) instruction that writes into the application flash memory sect ion must reside in the boot program section. status and control interrupt unit 32 x 8 general purpose registers alu data bus 8-bit data sram spi unit instruction register instruction decoder watchdog timer clock management eeprom portn control lines direct addressing indirect addressing i/o module n i/o module 1 program counter rom flash program memory
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 20 during interrupts and subroutine calls, the return address of the program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sr am, and consequently the stack size is onl y limited by the total sram size and the usage of the sram. all user programs must initialize the stack pointer (sp) in the reset routine (before subroutines or interrupts are executed). the sp is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate in terrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vect or address, the higher the priority. the i/o memory space contains 64 addresses for cpu periph eral functions as control registers, spi and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the circuit has extended i/o space from 0x60 - 0xff a nd sram where only the st/sts/std and ld/lds/ldd instructions can be used.
21 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 3.5 power management 3.5.1 overview the ic has four power domains: vs ? the unregulated battery voltage input. dvcc ? the internally regulated digital supply voltage. typical value is 1.35v. avcc ? the internally regulated rf frontend and xto supply. typical value is 1.85v. vs_pa ? the power amplifier supply has two applicati on modes depending on the battery voltage (vs) range: connected externally to the battery in 3v applications. generated by an internal regulator in 5v applications. the at5830 can be operated from v s = 1.9v to 3.6v (3v application) and from v s = 4.5v to 5.5v (5v application). for tx output powers above 10dbm applied in high band frequency rang es 836mhz to 928mhz, the minimum battery voltage is limited to 2.1v. figure 3-6. power supply management power management (common reference, voltage monitor vs_pa regulator avcc regulator port b spi port c 220nf 22nf 68nf vs_pa (only 3v operation) 2.2f avcc vs vs xtal1 ... level shifter rfin_lb rfin_hb spdt_rx spdt_ant spdt_tx rf_out ant_tune xtal2 ... ... data bus pb7 pb4 pc1 pc5 dvcc regulator avr cpu, avr peripherals, memories, rxdsp, txdsp and frc/src rf frontend and xto dvcc
ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 22 5. package information 4. ordering information extended type number package remarks ata5830-wnqw qfn32 5mm 5mm pb free ata5830n-wnqw qfn32 5mm 5mm pb free common dimensions (unit of measure = mm) package drawing contact: packagedrawings@atmel.com gpc symbol min nom max note 0.8 a 0.9 1 0.0 a1 0.02 0.05 0.15 a3 0.2 0.25 4.9 d 5 5.1 3.45 d2 3.6 3.75 4.9 e 5 5.1 3.45 e2 3.6 3.75 0.35 l 0.4 0.45 0.16 b 0.23 0.3 e 0.5 bsc drawing no. rev. title 6.543-5124.02-4 2 11/30/11 package: vqfn_5x5_32l exposed pad 3.6x3.6 dimensions in mm specifications according to din technical drawings top view partially plated surface d 1 8 32 pin 1 id e side view a3 a a1 b l z 10:1 bottom view e d2 9 1 8 16 17 24 25 32 e2 z two step singulation process
23 ata5830/ata5830n [summary datasheet] 9208fs?rke?06/13 6. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9208fs-rke-06/13 ? section 4 ?ordering information? on page 22 updated ? section 5 ?package information? on page 22 updated 9208es-rke-09/12 ? section 1.3.8 ?eeprom configuration? on page 4 updated 9208ds-rke-07/11 ? set datasheet from preliminary to standard 9208cs-rke-07/11 ? document completely redesigned 9208bs-rke-01/11 ? section 5 ?ordering information? on page 29 changed
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